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rev.1.4 rev.1.4 description the SRM2AW216LLBT 1/7 is a 131,072 words x 16-bit asynchronous, random access memory on a monolithic cmos chip. its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. the asynchronous and static nature of the memory requires no external clock and no refreshing circuit. it is possible to contorol the data width by the data byte control. 3-state output allows easy expansion of memory capacity. the temperature range of the SRM2AW216LLBT 1/7 is from ?0 to 85 c, and it is suitable for the industrial products. features fast access time ........................ 100ns (at 1.8v) / 70ns (at 2.2v) low supply current ..................... ll version completely static ........................ no clock required supply voltage ............................ 1.8v to 3.0v 3-state output with wired-or capability non-volatile storage with back-up batteries package ..................................... SRM2AW216LLBT tfbga-48 pin (tape csp) block diagram memory cell array 512 x 256 x 16 column gate i/o buffer 9 8 512 256 16 256x16 cs oe i/o1 i/o16 we a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 lb ub oe,ub,lb,we x decoder control logic cs control logic y decoder address buffer 2m-bit static ram pf988-09 SRM2AW216LLBT 1/7 super low voltage operation and low current consumption access time 100ns (1.8v) / 70ns (2.2v) 131,072 words x 16-bit asynchronous wide temperature range super low voltage operation products
rev.1.4 2 SRM2AW216LLBT 1/7 pin configuration a b c d e f g h 2 13456 lb oe a0 a3 a5 nc nc a14 a12 a9 a1 a4 a6 a7 a16 a15 a13 a10 a2 cs i/o2 i/o4 i/o5 i/o6 we a11 nc nc nc i/o1 i/o3 v dd v ss i/o7 i/o8 ub i/o9 i/o10 i/o11 i/o12 i/o12 i/o13 i/o14 nc a8 i/o15 i/o16 v ss v dd tfbga-48 pin top view (looking through part) SRM2AW216LLBT pin description a0 to a16 we oe cs lb ub i/o1 to 16 v dd v ss nc address input write enable output enable chip select lower byte enable upper byte enable data i/o power supply (1.8v to 3.0v) power supply (0v) no connection
rev.1.4 3 SRM2AW216LLBT 1/7 absolute maximum ratings supply voltage input voltage input/output voltage power dissipation operating temperature storage temperature soldering temperature and time parameter v dd v i v i/o p d t opr t stg t sol symbol ratings unit 0.5 to 3.6 0.5 * to v dd + 0.3 0.5 * to v dd + 0.3 0.5 40 to 85 65 to 150 260 c, 10s (at lead) (v ss =0v) * v i ,v i/o (min.) = 2.0v (when pulse width is less than 50ns) v v v w c c dc recommended operating conditions (ta = 40 to 85 c) parameter supply voltage input voltege symbol v dd v ss v ih v il v v v v * if pulse width is less than 50ns it is 2.0v min. 1.8 0.0 0.75v dd 0.3 * typ. 2.0 0.0 max. 2.2 0.0 v dd +0.3 0.3 min. 2.2 0.0 0.75v dd 0.3 * typ. 2.5 0.0 max. 3.0 0.0 v dd +0.3 0.3 unit v dd = 1.8 to 2.2v v dd = 2.2 to 3.0v electrical characteristics dc electrical characteristics parameter symbol conditions unit input leakage current standby supply current average operating current operating supply current high level output voltage i li i lo v oh i oh = 100 a i ol = 100 a low level output voltage v ol i dds i dds1 i dda i dda1 i ddo a (v ss =0v, ta = 40 to 85 c) v dd = 1.8 to 2.2v v dd = 2.2 to 3.0v v i = 0 to v dd lb and ub = v ih or cs = v ih or we = v il or oe = v ih , v i/o = 0 to v dd cs v dd 0.2v cs = v ih output leakage current 1.0 min. typ. *1 max. 1.0 a 1.0 1.0 ma 0.8 a 40 to 85 c 40 to 70 c 40 to 40 c 25 c 0.15 15 10 3.0 1.5 ma 20 30 ma 2.5 4 ma 2.5 4 v v v dd 0.2 0.2 1.0 min. typ. *2 max. 1.0 1.0 1.0 1.0 0.2 20 13.5 4.0 2.0 25 35 35 35 1.8 v dd 0.2 0.4 0.2 *1 : typical values are measured at ta = 25 c and v dd = 2.0v *2 : typical values are measured at ta = 25 c and v dd = 2.5v v i = v il or v ih i i/o = 0ma, t cyc = min. v i = v il or v ih i i/o = 0ma, t cyc = 1 s v i = v il or v ih i i/o = 0ma ll v dd 2.2v, i oh = -0.5ma v dd 2.2v, i ol = 0.5ma terminal capacitance (ta = 25 c, f = 1mhz) parameter symbol unit conditions address capacitance input capacitance i/o capacitance c add c i c i/o v add = 0v v i = 0v v i/o = 0v max. min. typ. note : this parameter is made by the inspection data of sample, not of all products 8 8 10 pf pf pf
rev.1.4 4 SRM2AW216LLBT 1/7 1ttl i/o c l *1 test conditions 1. input pulse level : 0.3v to 0.8v dd (1.8v to 3.0v) 2. t r = t f = 5ns 3. input and output timing reference levels :1/2v dd (1.8v to 3.0v) 4. output load : c l =50pf (includes jig capacitance) *2 test conditions 1. input pulse level : 0.3v to 0.8v dd (1.8v to 3.0v) 2. t r = t f = 5ns 3. input timing reference levels :1/2v dd (1.8v to 3.0v) 4. output timing reference levels : 200mv (the level changed from stable output voltage level) 5. output load :c l = 5pf (includes jig capacitance) ac electrical characteristics ? read cycle unit SRM2AW216LLBT 1 SRM2AW216LLBT 7 1.8 to 2.2v 2.2 to 3.0v min. 100 5 0 0 10 max. 100 100 60 60 40 40 40 min. 70 5 0 0 5 max. 70 70 40 40 30 30 30 parameter symbol test conditions (v ss = 0v, ta = 40 to 85 c) read cycle time address access time cs access time oe access time lb, ub access time cs output set time cs output floating lb, ub output set time lb, ub output floating oe output set time oe output floating output hold time t rc t acc t acs t oe t ab t clz t chz t blz t bhz t olz t ohz t oh 1 1 1 1 1 2 2 2 2 2 2 1 ns ns ns ns ns ns ns ns ns ns ns ns ? write cycle 1ttl i/o c l ? write cycle test conditions unit SRM2AW216LLBT 1 SRM2AW216LLBT 7 1.8 to 2.2v 2.2 to 3.0v 100 85 85 0 80 85 0 50 0 5 40 70 60 60 0 55 60 0 35 0 5 30 parameter symbol (v ss = 0v, ta = 40 to 85 c) write cycle time chip select time (cs) address enable time address setup time write pulse width lb, ub select time address hold time data setup time data hold time we output floating we output set time t wc t cw t aw t as t wp t bw t wr t dw t dh t whz t ow 1 1 1 1 1 1 1 1 1 2 2 ns ns ns ns ns ns ns ns ns ns ns min. max. min. max.
rev.1.4 5 SRM2AW216LLBT 1/7 timing chart read cycle *1 a0 to 16 lb, ub oe i/o1 to 16 (dout) t rc t acc t chz t acs t clz t ab t blz t bhz t oe t ohz t olz write cycle 1 (cs control) *2, *3 t wc high-z high-z t aw t cw t bw t wp t dw t wr t as t dh write cycle 3 (ub, lb control) *3 t wc t wp t bw t dw t wr t as t dh write cycle 2 (we control) *3 a0 to 16 cs lb, ub we i/o1 to 16 (dout) (din) t wc t cw t wp t dw t bw t wr t as t whz t ow t dh a0 to 16 cs lb, ub we i/o1 to 16 (dout) (din) lb, ub we cs a0 to 16 cs i/o1 to 16 (dout) (din) t oh t cw note : * 1 during read cycle time, w e is to be "high" level. * 2 in write cycle time that is controlled by c s , output buffer is to be "hi-z" state even if o e is "low" level. * 3 when output buffer is in output state, be careful that do not input the opposite signals to the output data. data retention characteristic with low voltage power supply parameter symbol conditions min. typ.* max. unit data retention supply voltage data retention curren data hold time operation recovery time v ddr i ddr t cdr t r 1.2 0 5 40 to 85 c 40 to 70 c 40 to 40 c +25 c 3.0 17 12 3.5 1.8 v a ns ms (v ss = 0v, ta = 40 to 85 c) v ddr = 2.5v cs v dd 0.2v 0.2 ll * : reference data at ta = 25 c data retention timing (cs control) v dd cs t cdr t r v ddr 1.2v cs v dd 0.2v 1.8v 1.8v data hold time v il v il 0.8xv dd 0.8xv dd
rev.1.4 6 SRM2AW216LLBT 1/7 functions truth table cs h l l l l l l l l x h l h l l h l x lb x h h l l h l l x ub x x x x x l l l h oe x x l l l h h h h we i/o1 to 8 i dd mode i dds , i dds1 i dda , i dda1 i dda , i dda1 i dda , i dda1 i dda , i dda1 i dda , i dda1 i dda , i dda1 i dda , i dda1 i dda , i dda1 high-z high-z data in high-z data in dataout high-z data out high-z i/o9 to 16 high-z high-z high-z data in data in high-z dataout data out high-z not selected output disable lower byte write upper byte write all byte write lower byte read upper byte read all byte read output disable x : high or low reading data it is possible to control the data width by l b and u b pins. (1) reading data from lower byte data is able to be read when the address is set while holding c s ="low", o e = "low", l b ="low" and w e = "high". (2) reading data from upper byte data is able to be read when the address is set while holding c s = "low", o e = "low", u b = "low" and w e ="high". (3) reading data from both bytes data is able to be read when the address is set while holding c s = "low", o e ="low", u b ="low", l b = "low", and w e = "high" since i/o pins are in "hi-z" state when o e = "high", the data bus line can be used for any other objective, then access time is apparently able to be cut down. writing data (1) writing data into lower byte there are the following three ways of writing data into memory. i) hold w e = "low", u b = "high" and l b = "low", set address and give "low" pulse to c s . ii) hold c s = "low", u b = "high" and l b = "low", set address and give "low" pulse to w e . iii) hold w e ="low", c s ="low" and u b = "high", set address and give "low" pulse to l b . anyway, data on i/o pins are latched up into the memory cell during c s ="low", w e ="low", and l b = "low". (2) writing data into upper byte there are the following three ways of writing data into the memory. i) hold w e = "low", l b = "high" and u b = "low", set address and give "low" pulse to c s . ii) hold c s = "low", l b = "high" and u b = "low", set address and give "low" pulse to w e . iii) hold w e ="low", c s ="low" and l b = "high", set address and give "low" pulse to u b . anyway, data on i/o pins are latched up into the memory cell during c s = "low", w e = "low", and u b = "low". (3)writing data into both bytes there are the following three ways of writing data into the memory. i) hold w e = "low", l b and u b = "low", set address and give "low" pulse to c s . ii) hold c s = "low", l b and u b = "low", set address and give "low" pulse to w e . iii) hold w e ="low" and c s ="low" , set address and give "low" pulse to l b and u b .
rev.1.4 7 SRM2AW216LLBT 1/7 anyway, data on i/o pins are latched up into the memory cell during c s = "low" , w e = "low", u b and l b = "low". as data i/o pins are in "hi-z" when c s ="high", o e ="high", or l b and u b ="high", the contention on the data bus can be avoided. but while i/o pins are in the output state, the data that is opposite to the output data should not be given standby mode when c s is "high" , the chip is in the standby mode (only retaining data operation). in this case data i/o pins are hi-z, and all inputs of addresses, w e , o e , u b , l b , and data are inhibited. when c s is in the range over v dd 0.2v, there is almost no current flow except through the high resistance parts of the memory. data retention at low voltage in case of the data retention in the stadby mode, the power supply can be gone down till the specified voltage. but it is impossible to write or read in this mode.
rev.1.4 8 SRM2AW216LLBT 1/7 unit : mm package dimensions tfbga-48 pin 123 456 h g f e d c b a 6 5 4 3 2 1 a b c d e f g h bottom view side view top view sram die base tape index 0.75 typ. 0.75 typ. 8.0 0.2 7.0 0.2 0.35 0.05 1.0 max. 0.2 +0.1 0.05
rev.1.4 9 SRM2AW216LLBT 1/7 characterics curves ? ? ? ? ? 5b? ? ? ? ? ? 5b? 7 %% 17 7 %% 17 /psnbmj[fe5 "$$ ? 5b7 %% 1?7 5 "$4 /psnbmj[fe5 "$$ ? 7 %% 7 %% 1?7 5 "$4 7 %% 7 5b1? 7 %% 7 /psnbmj[fe5 "$$ ? 7 %% 7 %% 1?7 5 "$4 5b1? ? 50 ? 30 ? 10 10 30 50 70 90 ? 40 ? 20 0 20 40 60 80 100 normalize i dds1 ? ta v dd 1 1.8 ? 2.2v 100 10 1 0.1 0.01 ta ? ? 50 ? 30 ? 10 10 30 50 70 90 ? 40 ? 20 0 20 40 60 80 100 100 10 1 0.1 0.01 ta ? v dd 1 2.0v normalize i dds1 ? ta v dd 1 2.2 ? 3.0v v dd 1 2.5v 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 ? 50 ? 30 ? 10 10 30 50 70 90 ? 40 ? 20 0 20 40 60 80 100 ta ? ? 50 ? 30 ? 10 10 30 50 70 90 ? 40 ? 20 0 20 40 60 80 100 ta ? normalized i dda ? ta v dd 1 1.8 ? 2.2v read write read write normalized i dda ? ta 2.2 ? 3.0v v dd 1 2.0v v dd 1 2.5v 1.7 1.8 1.9 2 21 2.2 2.3 v dd v normalized i dds1 ? v dd 1.8 ? 2.2v 10 1 0.1 ta 1 25 ? 2.1 2.3 2.5 2.7 2.9 3.1 2.2 2.4 2.6 2.8 3 v dd v 10 1 0.1 normalized i dds1 ? v dd 2.2 ? 3.0v ta 1 25 ? 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 1.7 1.8 1.9 2 21 2.2 2.3 2 2.2 2.4 2.6 2.8 3 3.2 2.1 2.3 2.5 2.7 2.9 3.1 v dd v v dd v normalized i dda ? v dd v dd 1 1.8 ? 2.2v write read ta 1 25 ? normalized i dda ? v dd v dd 1 2.2 ? 3.0v read write ta 1 25 ? /psnbmj[fe5 "$$ ? 5b7 %% 1?7 5 "$4
rev.1.4 10 SRM2AW216LLBT 1/7 /psnbmj[fe* 0) ? 7 0) 7 %% 1?7 /psnbmj[fe* %%" ? 'sfrvfodz7 %% 1?7 'sfrvfodz.)[u3$ uxd 'sfrvfodz.)[u3$ uxd 5b1? 7 %% 17 83*5& 3&"% 5b1? 7 %% 17 83*5& 3&"% /psnbmj[fe* %%" ? 'sfrvfodz7 %% 1?7 /psnbmj[fe* 0) ? 7 0) ?7 70)7 5b1? 7 %% 17 5b1? 7 %% 17 7 0) 7 5b1? 7 %% 17 /psnbmj[fe* 0- ? 7 0- ?7 7 0- 7 7 0- 7 /psnbmj[fe* 0- ? 7 0- ?7 5b1? 7 %% 17 5b1? 7 %% 17 /psnbmj[fe5 "$$ ? $ - ?7 5 "$4 $ - q' $ - q' /psnbmj[fe5 "$$ ? $ - ?7 5 "$4 5b1? 7 %% 17
SRM2AW216LLBT 1/7 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2000 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department europe & u.s.a. 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department asia 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 http://www.epson.co.jp/device/ epson electronic devices website rev.1.4 revised june, 2000 printed in japan t

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